In a power semiconductor device such as a vertical power metal oxide semiconductor field effect transistor (MOSFET) disclosed in Patent Document 1, as shown in FIGS. 1 and 2 of the Document, diodes are arranged in a line in a region adjacent to a peripheral portion of a cell region of the MOSFET, that is, to a gate pad portion. At a time when the MOSFET switches from the ON state to the OFF state, each of the diodes absorbs a hole that has been, at a time of forward biasing, injected into an N-type semiconductor layer at the drain side of a well and a P-base shown in FIG. 2 of the Document. Therefore, the above-mentioned structure shown in the Document can prevent a parasitic transistor shown in FIG. 3 of the Document from turning on at a time when the MOSFET switches from forward bias to reverse bias, thus preventing destruction of an element due to a high current concentration.
In the above-mentioned structure of the Document, as shown in FIG. 2, the P-base that is a well of the MOSFET is electrically connected to a source electrode via a back gate.
A method is also known in which breakdown is suppressed by electrically connecting a P-type diffusion region having a large area of a power semiconductor device to neither of the gate and the source (for example, Patent Document 2).
[Patent Document 1] Japanese Patent Application Laid-Open No. 1993-198816 (FIGS. 1 to 3)
[Patent Document 2] Japanese Patent Application Laid-Open No. 1992-363068 (FIG. 1)